Compared with two-level inverters, multi-level inverters, such as a three-level inverter, for example, can achieve a better output signal waveform. In a multilevel-level inverter, the DC link may be divided into two halves by a neutral point (NP). Output phases of the inverter may be switched to a positive pole, a negative pole or the neutral point of the DC link. This allows use of smaller voltage steps in output voltage generation. FIG. 1 shows a conceptual diagram of a three-level, three-phase inverter.
In FIG. 1, a DC link 11 includes two capacitors C1 and C2 connected in series. The DC link 11 includes a positive pole DC+, a negative pole DC−, and a neutral point NP. The voltage uDC over the DC link is the sum of voltages uC1 and uC2 over the capacitors C1 and C2. Each capacitor forms one half of the DC link. The inverter output voltage is generated by connecting each of phase lines 12 of a load 13 to the positive pole DC+, the negative pole DC− or the neutral point NP. The load 13 may be an electric motor or a generator, for example.
FIG. 1 shows a high-side current ihi, i.e., a current from the positive pole DC+ to the load 13, and a low-side current ilo, i.e., a current from the negative pole DC− to the load 13. iNP represents a current from the neutral point NP to the load 13. The magnitude of neutral point current iNP equals the difference between magnitudes of the high-side current ihi and low-side current ilo.
The phase lines 12 are connected to the DC link in FIG. 1 through switching arrangements 14 which may include a plurality of semiconductor switches, such as IGBTs or MOSFETs.
Topologies including a neutral point dividing the DC link into two halves, as in FIG. 1, may involve a modulation strategy which keeps the voltages over the halves in balance. In FIG. 1, this means that the high- and low-side capacitor voltages uC1 and uC2 are maintained as close as possible to each other in all situations. In this document, balancing of the voltages over the halves of the DC link may also be referred to as neutral point (NP) voltage balancing.
One known NP voltage balancing method utilizes a common-mode (CM) voltage control based on selecting the applied switching patterns.
A three-level inverter, such as that in FIG. 1, may have redundancy in the switching patterns of the switches of the inverter bridge. In this context, the switching pattern refers to a combination of switching states of the switches. The switches, each set to a (conducting or non-conducting) state, produce an output voltage vector.
For example, one desired output voltage vector may be achieved with two switching patterns: a switching pattern coupling the load to the voltage potential of the higher half of the DC link, and another coupling the load to the voltage potential of the lower half of the DC link. By choosing which switching combinations are used, the common mode voltage may be controlled.
In the above voltage balancing method, a CM voltage control reference controlling the common mode voltage is adjusted on the basis of the output power and an NP voltage unbalance, i.e. a difference between uC1 and uC2. For example, if the NP voltage is too low (uC1>uC2 in FIG. 1) and the actual power is positive (i.e. the power is fed from the inverter to a load), the CM voltage reference may be increased to a positive value thereby causing the inverter to modulate in such a way that an average duration of switching patterns connected to the positive DC link pole DC+ exceeds the duration of patterns connected to the negative DC link pole DC−. This difference in durations, in turn, increases the current ihi of the positive pole DC+ and decreases current ilo of the negative pole DC−. The NP current iNP becomes negative, which decreases uC1 voltage and balances the NP voltage. Correspondingly, if the NP voltage is too high or the output power is negative, the CM voltage may be decreased to a negative value in order to balance the NP voltage.
If the output power is high enough so that the direction of power flow between the inverter and the load can be detected, the NP voltage can be balanced in a robust manner.
However, if the actual power is low, the NP voltage may become unstable as power estimation errors may cause wrongly detected power flow directions. Also, if the actual power is zero and the NP potential is unbalanced, the method may not be able to stabilize the NP potential as there is no power available for balancing.